Go to the documentation of this file. 1 #ifndef XTF_X86_PROCESSOR_H 2 #define XTF_X86_PROCESSOR_H 7 #define X86_EFLAGS_CF 0x00000001 8 #define X86_EFLAGS_MBS 0x00000002 9 #define X86_EFLAGS_PF 0x00000004 10 #define X86_EFLAGS_AF 0x00000010 11 #define X86_EFLAGS_ZF 0x00000040 12 #define X86_EFLAGS_SF 0x00000080 13 #define X86_EFLAGS_TF 0x00000100 14 #define X86_EFLAGS_IF 0x00000200 15 #define X86_EFLAGS_DF 0x00000400 16 #define X86_EFLAGS_OF 0x00000800 17 #define X86_EFLAGS_IOPL 0x00003000 18 #define X86_EFLAGS_NT 0x00004000 19 #define X86_EFLAGS_RF 0x00010000 20 #define X86_EFLAGS_VM 0x00020000 21 #define X86_EFLAGS_AC 0x00040000 22 #define X86_EFLAGS_VIF 0x00080000 23 #define X86_EFLAGS_VIP 0x00100000 24 #define X86_EFLAGS_ID 0x00200000 29 #define X86_CR0_PE 0x00000001 30 #define X86_CR0_MP 0x00000002 31 #define X86_CR0_EM 0x00000004 32 #define X86_CR0_TS 0x00000008 33 #define X86_CR0_ET 0x00000010 34 #define X86_CR0_NE 0x00000020 35 #define X86_CR0_WP 0x00010000 36 #define X86_CR0_AM 0x00040000 37 #define X86_CR0_NW 0x20000000 38 #define X86_CR0_CD 0x40000000 39 #define X86_CR0_PG 0x80000000 44 #define X86_CR4_VME 0x00000001 45 #define X86_CR4_PVI 0x00000002 46 #define X86_CR4_TSD 0x00000004 47 #define X86_CR4_DE 0x00000008 48 #define X86_CR4_PSE 0x00000010 49 #define X86_CR4_PAE 0x00000020 50 #define X86_CR4_MCE 0x00000040 51 #define X86_CR4_PGE 0x00000080 52 #define X86_CR4_PCE 0x00000100 53 #define X86_CR4_OSFXSR 0x00000200 54 #define X86_CR4_OSXMMEXCPT 0x00000400 55 #define X86_CR4_UMIP 0x00000800 56 #define X86_CR4_VMXE 0x00002000 57 #define X86_CR4_SMXE 0x00004000 58 #define X86_CR4_FSGSBASE 0x00010000 59 #define X86_CR4_PCIDE 0x00020000 60 #define X86_CR4_OSXSAVE 0x00040000 61 #define X86_CR4_SMEP 0x00100000 62 #define X86_CR4_SMAP 0x00200000 68 #define XSTATE_FP (1ULL << _XSTATE_FP) 70 #define XSTATE_SSE (1ULL << _XSTATE_SSE) 72 #define XSTATE_YMM (1ULL << _XSTATE_YMM) 73 #define _XSTATE_BNDREGS 3 74 #define XSTATE_BNDREGS (1ULL << _XSTATE_BNDREGS) 75 #define _XSTATE_BNDCSR 4 76 #define XSTATE_BNDCSR (1ULL << _XSTATE_BNDCSR) 77 #define _XSTATE_OPMASK 5 78 #define XSTATE_OPMASK (1ULL << _XSTATE_OPMASK) 80 #define XSTATE_ZMM (1ULL << _XSTATE_ZMM) 81 #define _XSTATE_HI_ZMM 7 82 #define XSTATE_HI_ZMM (1ULL << _XSTATE_HI_ZMM) 83 #define _XSTATE_PKRU 9 84 #define XSTATE_PKRU (1ULL << _XSTATE_PKRU) 85 #define _XSTATE_LWP 62 86 #define XSTATE_LWP (1ULL << _XSTATE_LWP) 91 #define X86_MXCSR_IE 0x00000001 92 #define X86_MXCSR_DE 0x00000002 93 #define X86_MXCSR_ZE 0x00000004 94 #define X86_MXCSR_OE 0x00000008 95 #define X86_MXCSR_UE 0x00000010 96 #define X86_MXCSR_PE 0x00000020 97 #define X86_MXCSR_STATUS_MASK 0x0000003f 104 #define X86_EXC_NMI 2 111 #define X86_EXC_CSO 9 112 #define X86_EXC_TS 10 113 #define X86_EXC_NP 11 114 #define X86_EXC_SS 12 115 #define X86_EXC_GP 13 116 #define X86_EXC_PF 14 117 #define X86_EXC_SPV 15 118 #define X86_EXC_MF 16 119 #define X86_EXC_AC 17 120 #define X86_EXC_MC 18 121 #define X86_EXC_XM 19 122 #define X86_EXC_VE 20 125 #define X86_EXC_HAVE_EC ((1 << X86_EXC_DF) | (1 << X86_EXC_TS) | \ 126 (1 << X86_EXC_NP) | (1 << X86_EXC_SS) | \ 127 (1 << X86_EXC_GP) | (1 << X86_EXC_PF) | \ 131 #define X86_EXC_FAULTS ((1 << X86_EXC_DE) | (1 << X86_EXC_BR) | \ 132 (1 << X86_EXC_UD) | (1 << X86_EXC_NM) | \ 133 (1 << X86_EXC_CSO) | (1 << X86_EXC_TS) | \ 134 (1 << X86_EXC_NP) | (1 << X86_EXC_SS) | \ 135 (1 << X86_EXC_GP) | (1 << X86_EXC_PF) | \ 136 (1 << X86_EXC_MF) | (1 << X86_EXC_AC) | \ 137 (1 << X86_EXC_XM) | (1 << X86_EXC_VE)) 140 #define X86_EXC_INTERRUPTS (1 << X86_EXC_NMI) 143 #define X86_EXC_TRAPS ((1 << X86_EXC_BP) | (1 << X86_EXC_OF)) 146 #define X86_EXC_ABORTS ((1 << X86_EXC_DF) | (1 << X86_EXC_MC)) 149 #define X86_NR_RESERVED_VECTORS 32 155 #define X86_EC_EXT (1U << 0) 156 #define X86_EC_IDT (1U << 1) 157 #define X86_EC_TI (1U << 2) 160 #define X86_EC_TABLE_MASK (3 << 1) 161 #define X86_EC_SEL_SHIFT 3 162 #define X86_EC_SEL_MASK (~0U << X86_EC_SEL_SHIFT) 164 #define X86_EC_LDT X86_EC_TI 167 #define X86_PFEC_PRESENT (1U << 0) 168 #define X86_PFEC_WRITE (1U << 1) 169 #define X86_PFEC_USER (1U << 2) 170 #define X86_PFEC_RSVD (1U << 3) 171 #define X86_PFEC_INSN (1U << 4) 172 #define X86_PFEC_PK (1U << 5) 175 #define X86_PFEC_P X86_PFEC_PRESENT 176 #define X86_PFEC_W X86_PFEC_WRITE 177 #define X86_PFEC_U X86_PFEC_USER 178 #define X86_PFEC_R X86_PFEC_RSVD 179 #define X86_PFEC_I X86_PFEC_INSN 180 #define X86_PFEC_K X86_PFEC_PK 186 #define X86_SEL_TI (1U << 2) 189 #define X86_SEL_RPL_MASK 3 190 #define X86_SEL_GDT 0 191 #define X86_SEL_LDT X86_SEL_TI