Click a patch. Blue outline = what it needs
(ancestors); vermilion = what needs it (descendants). Click again or press
Clear to reset.
Legend
verified dependency
inferred (verify during group review)
gold arrow: completes an end goal (hexagons). Each goal is drawn beside the group that achieves it; together the four constitute the ASI end state (guest-owned data not reachable from other contexts).
green node border: vetted so far (status shown on selection)
double border: posted to xen-devel (thread link on selection)
blue border and ✓ in the label: carries a Reviewed-by (tags shown on selection)
Dependencies already implied by a drawn path are recorded but not drawn; the click-cone includes them.
Postings
part 1 (Aug 2026) — nodes d05–d10: cover letter (threads via the sidebar; links resolve on lore once posted)
part 2 (Sep 2026) — nodes d04–d17: cover letter (threads via the sidebar; links resolve on lore once posted)
Open items
Node numbers are written dNN and name positions in the current series order shown here; they are stable within one revision of this page but are not the patch numbers of any particular posting (a posted patch 12/ need not be d12).
9 Sep 2026 -- the multi-page transient maps (d37-d39) and the FPU / XSAVE area handling (d40-d46) now follow the directmap removal directly, ahead of the rendezvous and per-CPU stack work (d47-d62): the on-demand directmap, the per-vCPU address space and the XSAVE-area relocation then form a self-contained increment, and the per-CPU stack work builds on top of it.
8 Sep 2026 -- a standalone fix, "x86/pv: drop the old GDT frames only after their translations are flushed" (d03), now heads the series so that it can be backported on its own; the part-2 posting's fourteen patches, d03-d16 in its cover letter, are d04-d17 on this page.
This graph is a work in progress: it maps the whole intended series, and dependency lines (especially dashed ones) may still change as later groups are vetted.
Posting model: a rolling series. Patches are posted from the front as they become ready and dropped once committed; new ones are appended as they mature. "A later patch" in a message may therefore mean "next round in this series".
Groups are not posting units. Some stand alone (d04-d10 retire the stashed GDT/LDT L1 pointers; the interface simplification could go by itself); others only make sense with their consumers (the per-vCPU tables without their users are infrastructure with no user).
The series head, "x86: always park offline CPUs", is Jan Beulich's own upstream posting (26 Aug 2026), which this series depends on and carries unchanged until it lands.
Edges are logical dependencies -- an edge means the pair cannot compose in the other order without redesign -- plus a few purpose edges ("A exists to make B reviewable"). Dashed edges are inferred from titles/messages and should be confirmed as their groups are reviewed. Symbol hits inside docs/designs/asi.md are index updates, not dependencies.
Known commuting pairs deliberately carry no edge: e.g. the GDT and LDT conversions versus the destroy() parameter switch -- either order composes, with one-line adapters on whichever comes second.
The per-vCPU address space and mapcache is delivered jointly by the per-vCPU L3, the per-vCPU mapcache and the unique root L4; the cluster is named for that effect, and is what per-CPU stacks, the unified mapcache and the state window depend on (cluster edges).
The Arm patches are parked, not part of this series; the design doc's arm64 work item reads TODO accordingly.
Source of truth: gen-depgraph.py (same directory);
positions read live from stg series; regenerate with
python3 gen-depgraph.py.