Xen Test Framework
cpufeatureset.h
Go to the documentation of this file.
1 /*
2  * Xen x86 public cpufeatureset interface
3  */
4 
5 #ifndef XEN_PUBLIC_ARCH_X86_CPUFEATURESET_H
6 #define XEN_PUBLIC_ARCH_X86_CPUFEATURESET_H
7 
8 /*
9  * A featureset is a bitmap of x86 features, represented as a collection of
10  * 32bit words.
11  *
12  * Words are as specified in vendors programming manuals, and shall not
13  * contain any synthesied values. New words may be added to the end of
14  * featureset.
15  *
16  * All featureset words currently originate from leaves specified for the
17  * CPUID instruction, but this is not preclude other sources of information.
18  */
19 
20 /* Intel-defined CPU features, CPUID level 0x00000001.edx, word 0 */
21 #define X86_FEATURE_FPU (0*32+ 0) /* Onboard FPU */
22 #define X86_FEATURE_VME (0*32+ 1) /* Virtual Mode Extensions */
23 #define X86_FEATURE_DE (0*32+ 2) /* Debugging Extensions */
24 #define X86_FEATURE_PSE (0*32+ 3) /* Page Size Extensions */
25 #define X86_FEATURE_TSC (0*32+ 4) /* Time Stamp Counter */
26 #define X86_FEATURE_MSR (0*32+ 5) /* Model-Specific Registers, RDMSR, WRMSR */
27 #define X86_FEATURE_PAE (0*32+ 6) /* Physical Address Extensions */
28 #define X86_FEATURE_MCE (0*32+ 7) /* Machine Check Architecture */
29 #define X86_FEATURE_CX8 (0*32+ 8) /* CMPXCHG8 instruction */
30 #define X86_FEATURE_APIC (0*32+ 9) /* Onboard APIC */
31 #define X86_FEATURE_SEP (0*32+11) /* SYSENTER/SYSEXIT */
32 #define X86_FEATURE_MTRR (0*32+12) /* Memory Type Range Registers */
33 #define X86_FEATURE_PGE (0*32+13) /* Page Global Enable */
34 #define X86_FEATURE_MCA (0*32+14) /* Machine Check Architecture */
35 #define X86_FEATURE_CMOV (0*32+15) /* CMOV instruction (FCMOVCC and FCOMI too if FPU present) */
36 #define X86_FEATURE_PAT (0*32+16) /* Page Attribute Table */
37 #define X86_FEATURE_PSE36 (0*32+17) /* 36-bit PSEs */
38 #define X86_FEATURE_CLFLUSH (0*32+19) /* CLFLUSH instruction */
39 #define X86_FEATURE_DS (0*32+21) /* Debug Store */
40 #define X86_FEATURE_ACPI (0*32+22) /* ACPI via MSR */
41 #define X86_FEATURE_MMX (0*32+23) /* Multimedia Extensions */
42 #define X86_FEATURE_FXSR (0*32+24) /* FXSAVE and FXRSTOR instructions */
43 #define X86_FEATURE_SSE (0*32+25) /* Streaming SIMD Extensions */
44 #define X86_FEATURE_SSE2 (0*32+26) /* Streaming SIMD Extensions-2 */
45 #define X86_FEATURE_HTT (0*32+28) /* Hyper-Threading Technology */
46 #define X86_FEATURE_TM1 (0*32+29) /* Thermal Monitor 1 */
47 #define X86_FEATURE_PBE (0*32+31) /* Pending Break Enable */
48 
49 /* Intel-defined CPU features, CPUID level 0x00000001.ecx, word 1 */
50 #define X86_FEATURE_SSE3 (1*32+ 0) /* Streaming SIMD Extensions-3 */
51 #define X86_FEATURE_PCLMULQDQ (1*32+ 1) /* Carry-less mulitplication */
52 #define X86_FEATURE_DTES64 (1*32+ 2) /* 64-bit Debug Store */
53 #define X86_FEATURE_MONITOR (1*32+ 3) /* Monitor/Mwait support */
54 #define X86_FEATURE_DSCPL (1*32+ 4) /* CPL Qualified Debug Store */
55 #define X86_FEATURE_VMX (1*32+ 5) /* Virtual Machine Extensions */
56 #define X86_FEATURE_SMX (1*32+ 6) /* Safer Mode Extensions */
57 #define X86_FEATURE_EIST (1*32+ 7) /* Enhanced SpeedStep */
58 #define X86_FEATURE_TM2 (1*32+ 8) /* Thermal Monitor 2 */
59 #define X86_FEATURE_SSSE3 (1*32+ 9) /* Supplemental Streaming SIMD Extensions-3 */
60 #define X86_FEATURE_FMA (1*32+12) /* Fused Multiply Add */
61 #define X86_FEATURE_CX16 (1*32+13) /* CMPXCHG16B */
62 #define X86_FEATURE_XTPR (1*32+14) /* Send Task Priority Messages */
63 #define X86_FEATURE_PDCM (1*32+15) /* Perf/Debug Capability MSR */
64 #define X86_FEATURE_PCID (1*32+17) /* Process Context ID */
65 #define X86_FEATURE_DCA (1*32+18) /* Direct Cache Access */
66 #define X86_FEATURE_SSE4_1 (1*32+19) /* Streaming SIMD Extensions 4.1 */
67 #define X86_FEATURE_SSE4_2 (1*32+20) /* Streaming SIMD Extensions 4.2 */
68 #define X86_FEATURE_X2APIC (1*32+21) /* Extended xAPIC */
69 #define X86_FEATURE_MOVBE (1*32+22) /* movbe instruction */
70 #define X86_FEATURE_POPCNT (1*32+23) /* POPCNT instruction */
71 #define X86_FEATURE_TSC_DEADLINE (1*32+24) /* TSC Deadline Timer */
72 #define X86_FEATURE_AESNI (1*32+25) /* AES instructions */
73 #define X86_FEATURE_XSAVE (1*32+26) /* XSAVE/XRSTOR/XSETBV/XGETBV */
74 #define X86_FEATURE_OSXSAVE (1*32+27) /* OSXSAVE */
75 #define X86_FEATURE_AVX (1*32+28) /* Advanced Vector Extensions */
76 #define X86_FEATURE_F16C (1*32+29) /* Half-precision convert instruction */
77 #define X86_FEATURE_RDRAND (1*32+30) /* Digital Random Number Generator */
78 #define X86_FEATURE_HYPERVISOR (1*32+31) /* Running under some hypervisor */
79 
80 /* AMD-defined CPU features, CPUID level 0x80000001.edx, word 2 */
81 #define X86_FEATURE_SYSCALL (2*32+11) /* SYSCALL/SYSRET */
82 #define X86_FEATURE_NX (2*32+20) /* Execute Disable */
83 #define X86_FEATURE_MMXEXT (2*32+22) /* AMD MMX extensions */
84 #define X86_FEATURE_FFXSR (2*32+25) /* FFXSR instruction optimizations */
85 #define X86_FEATURE_PAGE1GB (2*32+26) /* 1Gb large page support */
86 #define X86_FEATURE_RDTSCP (2*32+27) /* RDTSCP */
87 #define X86_FEATURE_LM (2*32+29) /* Long Mode (x86-64) */
88 #define X86_FEATURE_3DNOWEXT (2*32+30) /* AMD 3DNow! extensions */
89 #define X86_FEATURE_3DNOW (2*32+31) /* 3DNow! */
90 
91 /* AMD-defined CPU features, CPUID level 0x80000001.ecx, word 3 */
92 #define X86_FEATURE_LAHF_LM (3*32+ 0) /* LAHF/SAHF in long mode */
93 #define X86_FEATURE_CMP_LEGACY (3*32+ 1) /* If yes HyperThreading not valid */
94 #define X86_FEATURE_SVM (3*32+ 2) /* Secure virtual machine */
95 #define X86_FEATURE_EXTAPIC (3*32+ 3) /* Extended APIC space */
96 #define X86_FEATURE_CR8_LEGACY (3*32+ 4) /* CR8 in 32-bit mode */
97 #define X86_FEATURE_ABM (3*32+ 5) /* Advanced bit manipulation */
98 #define X86_FEATURE_SSE4A (3*32+ 6) /* SSE-4A */
99 #define X86_FEATURE_MISALIGNSSE (3*32+ 7) /* Misaligned SSE mode */
100 #define X86_FEATURE_3DNOWPREFETCH (3*32+ 8) /* 3DNow prefetch instructions */
101 #define X86_FEATURE_OSVW (3*32+ 9) /* OS Visible Workaround */
102 #define X86_FEATURE_IBS (3*32+10) /* Instruction Based Sampling */
103 #define X86_FEATURE_XOP (3*32+11) /* extended AVX instructions */
104 #define X86_FEATURE_SKINIT (3*32+12) /* SKINIT/STGI instructions */
105 #define X86_FEATURE_WDT (3*32+13) /* Watchdog timer */
106 #define X86_FEATURE_LWP (3*32+15) /* Light Weight Profiling */
107 #define X86_FEATURE_FMA4 (3*32+16) /* 4 operands MAC instructions */
108 #define X86_FEATURE_NODEID_MSR (3*32+19) /* NodeId MSR */
109 #define X86_FEATURE_TBM (3*32+21) /* trailing bit manipulations */
110 #define X86_FEATURE_TOPOEXT (3*32+22) /* topology extensions CPUID leafs */
111 #define X86_FEATURE_DBEXT (3*32+26) /* data breakpoint extension */
112 #define X86_FEATURE_MONITORX (3*32+29) /* MONITOR extension (MONITORX/MWAITX) */
113 
114 /* Intel-defined CPU features, CPUID level 0x0000000D:1.eax, word 4 */
115 #define X86_FEATURE_XSAVEOPT (4*32+ 0) /* XSAVEOPT instruction */
116 #define X86_FEATURE_XSAVEC (4*32+ 1) /* XSAVEC/XRSTORC instructions */
117 #define X86_FEATURE_XGETBV1 (4*32+ 2) /* XGETBV with %ecx=1 */
118 #define X86_FEATURE_XSAVES (4*32+ 3) /* XSAVES/XRSTORS instructions */
119 
120 /* Intel-defined CPU features, CPUID level 0x00000007:0.ebx, word 5 */
121 #define X86_FEATURE_FSGSBASE (5*32+ 0) /* {RD,WR}{FS,GS}BASE instructions */
122 #define X86_FEATURE_TSC_ADJUST (5*32+ 1) /* TSC_ADJUST MSR available */
123 #define X86_FEATURE_SGX (5*32+ 2) /* Software Guard extensions */
124 #define X86_FEATURE_BMI1 (5*32+ 3) /* 1st bit manipulation extensions */
125 #define X86_FEATURE_HLE (5*32+ 4) /* Hardware Lock Elision */
126 #define X86_FEATURE_AVX2 (5*32+ 5) /* AVX2 instructions */
127 #define X86_FEATURE_FDP_EXCP_ONLY (5*32+ 6) /* x87 FDP only updated on exception. */
128 #define X86_FEATURE_SMEP (5*32+ 7) /* Supervisor Mode Execution Protection */
129 #define X86_FEATURE_BMI2 (5*32+ 8) /* 2nd bit manipulation extensions */
130 #define X86_FEATURE_ERMS (5*32+ 9) /* Enhanced REP MOVSB/STOSB */
131 #define X86_FEATURE_INVPCID (5*32+10) /* Invalidate Process Context ID */
132 #define X86_FEATURE_RTM (5*32+11) /* Restricted Transactional Memory */
133 #define X86_FEATURE_PQM (5*32+12) /* Platform QoS Monitoring */
134 #define X86_FEATURE_NO_FPU_SEL (5*32+13) /* FPU CS/DS stored as zero */
135 #define X86_FEATURE_MPX (5*32+14) /* Memory Protection Extensions */
136 #define X86_FEATURE_PQE (5*32+15) /* Platform QoS Enforcement */
137 #define X86_FEATURE_RDSEED (5*32+18) /* RDSEED instruction */
138 #define X86_FEATURE_ADX (5*32+19) /* ADCX, ADOX instructions */
139 #define X86_FEATURE_SMAP (5*32+20) /* Supervisor Mode Access Prevention */
140 #define X86_FEATURE_PCOMMIT (5*32+22) /* PCOMMIT instruction */
141 #define X86_FEATURE_CLFLUSHOPT (5*32+23) /* CLFLUSHOPT instruction */
142 #define X86_FEATURE_CLWB (5*32+24) /* CLWB instruction */
143 #define X86_FEATURE_SHA (5*32+29) /* SHA1 & SHA256 instructions */
144 
145 /* Intel-defined CPU features, CPUID level 0x00000007:0.ecx, word 6 */
146 #define X86_FEATURE_PREFETCHWT1 (6*32+ 0) /* PREFETCHWT1 instruction */
147 #define X86_FEATURE_UMIP (6*32+ 2) /* User-Mode Instruction Prevention */
148 #define X86_FEATURE_PKU (6*32+ 3) /* Protection Keys for Userspace */
149 #define X86_FEATURE_OSPKE (6*32+ 4) /* OS Protection Keys Enable */
150 
151 /* AMD-defined CPU features, CPUID level 0x80000007.edx, word 7 */
152 #define X86_FEATURE_ITSC (7*32+ 8) /* Invariant TSC */
153 #define X86_FEATURE_EFRO (7*32+10) /* APERF/MPERF Read Only interface */
154 
155 /* AMD-defined CPU features, CPUID level 0x80000008.ebx, word 8 */
156 #define X86_FEATURE_CLZERO (8*32+ 0) /* CLZERO instruction */
157 
158 #endif /* XEN_PUBLIC_ARCH_X86_CPUFEATURESET_H */
159 
160 /*
161  * Local variables:
162  * mode: C
163  * c-file-style: "BSD"
164  * c-basic-offset: 4
165  * tab-width: 4
166  * indent-tabs-mode: nil
167  * End:
168  */
Generated by   doxygen 1.8.13