Xen Test Framework
Macros
cpufeatureset.h File Reference
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Macros

#define X86_FEATURE_FPU   (0*32+ 0) /* Onboard FPU */
 
#define X86_FEATURE_VME   (0*32+ 1) /* Virtual Mode Extensions */
 
#define X86_FEATURE_DE   (0*32+ 2) /* Debugging Extensions */
 
#define X86_FEATURE_PSE   (0*32+ 3) /* Page Size Extensions */
 
#define X86_FEATURE_TSC   (0*32+ 4) /* Time Stamp Counter */
 
#define X86_FEATURE_MSR   (0*32+ 5) /* Model-Specific Registers, RDMSR, WRMSR */
 
#define X86_FEATURE_PAE   (0*32+ 6) /* Physical Address Extensions */
 
#define X86_FEATURE_MCE   (0*32+ 7) /* Machine Check Architecture */
 
#define X86_FEATURE_CX8   (0*32+ 8) /* CMPXCHG8 instruction */
 
#define X86_FEATURE_APIC   (0*32+ 9) /* Onboard APIC */
 
#define X86_FEATURE_SEP   (0*32+11) /* SYSENTER/SYSEXIT */
 
#define X86_FEATURE_MTRR   (0*32+12) /* Memory Type Range Registers */
 
#define X86_FEATURE_PGE   (0*32+13) /* Page Global Enable */
 
#define X86_FEATURE_MCA   (0*32+14) /* Machine Check Architecture */
 
#define X86_FEATURE_CMOV   (0*32+15) /* CMOV instruction (FCMOVCC and FCOMI too if FPU present) */
 
#define X86_FEATURE_PAT   (0*32+16) /* Page Attribute Table */
 
#define X86_FEATURE_PSE36   (0*32+17) /* 36-bit PSEs */
 
#define X86_FEATURE_CLFLUSH   (0*32+19) /* CLFLUSH instruction */
 
#define X86_FEATURE_DS   (0*32+21) /* Debug Store */
 
#define X86_FEATURE_ACPI   (0*32+22) /* ACPI via MSR */
 
#define X86_FEATURE_MMX   (0*32+23) /* Multimedia Extensions */
 
#define X86_FEATURE_FXSR   (0*32+24) /* FXSAVE and FXRSTOR instructions */
 
#define X86_FEATURE_SSE   (0*32+25) /* Streaming SIMD Extensions */
 
#define X86_FEATURE_SSE2   (0*32+26) /* Streaming SIMD Extensions-2 */
 
#define X86_FEATURE_HTT   (0*32+28) /* Hyper-Threading Technology */
 
#define X86_FEATURE_TM1   (0*32+29) /* Thermal Monitor 1 */
 
#define X86_FEATURE_PBE   (0*32+31) /* Pending Break Enable */
 
#define X86_FEATURE_SSE3   (1*32+ 0) /* Streaming SIMD Extensions-3 */
 
#define X86_FEATURE_PCLMULQDQ   (1*32+ 1) /* Carry-less mulitplication */
 
#define X86_FEATURE_DTES64   (1*32+ 2) /* 64-bit Debug Store */
 
#define X86_FEATURE_MONITOR   (1*32+ 3) /* Monitor/Mwait support */
 
#define X86_FEATURE_DSCPL   (1*32+ 4) /* CPL Qualified Debug Store */
 
#define X86_FEATURE_VMX   (1*32+ 5) /* Virtual Machine Extensions */
 
#define X86_FEATURE_SMX   (1*32+ 6) /* Safer Mode Extensions */
 
#define X86_FEATURE_EIST   (1*32+ 7) /* Enhanced SpeedStep */
 
#define X86_FEATURE_TM2   (1*32+ 8) /* Thermal Monitor 2 */
 
#define X86_FEATURE_SSSE3   (1*32+ 9) /* Supplemental Streaming SIMD Extensions-3 */
 
#define X86_FEATURE_FMA   (1*32+12) /* Fused Multiply Add */
 
#define X86_FEATURE_CX16   (1*32+13) /* CMPXCHG16B */
 
#define X86_FEATURE_XTPR   (1*32+14) /* Send Task Priority Messages */
 
#define X86_FEATURE_PDCM   (1*32+15) /* Perf/Debug Capability MSR */
 
#define X86_FEATURE_PCID   (1*32+17) /* Process Context ID */
 
#define X86_FEATURE_DCA   (1*32+18) /* Direct Cache Access */
 
#define X86_FEATURE_SSE4_1   (1*32+19) /* Streaming SIMD Extensions 4.1 */
 
#define X86_FEATURE_SSE4_2   (1*32+20) /* Streaming SIMD Extensions 4.2 */
 
#define X86_FEATURE_X2APIC   (1*32+21) /* Extended xAPIC */
 
#define X86_FEATURE_MOVBE   (1*32+22) /* movbe instruction */
 
#define X86_FEATURE_POPCNT   (1*32+23) /* POPCNT instruction */
 
#define X86_FEATURE_TSC_DEADLINE   (1*32+24) /* TSC Deadline Timer */
 
#define X86_FEATURE_AESNI   (1*32+25) /* AES instructions */
 
#define X86_FEATURE_XSAVE   (1*32+26) /* XSAVE/XRSTOR/XSETBV/XGETBV */
 
#define X86_FEATURE_OSXSAVE   (1*32+27) /* OSXSAVE */
 
#define X86_FEATURE_AVX   (1*32+28) /* Advanced Vector Extensions */
 
#define X86_FEATURE_F16C   (1*32+29) /* Half-precision convert instruction */
 
#define X86_FEATURE_RDRAND   (1*32+30) /* Digital Random Number Generator */
 
#define X86_FEATURE_HYPERVISOR   (1*32+31) /* Running under some hypervisor */
 
#define X86_FEATURE_SYSCALL   (2*32+11) /* SYSCALL/SYSRET */
 
#define X86_FEATURE_NX   (2*32+20) /* Execute Disable */
 
#define X86_FEATURE_MMXEXT   (2*32+22) /* AMD MMX extensions */
 
#define X86_FEATURE_FFXSR   (2*32+25) /* FFXSR instruction optimizations */
 
#define X86_FEATURE_PAGE1GB   (2*32+26) /* 1Gb large page support */
 
#define X86_FEATURE_RDTSCP   (2*32+27) /* RDTSCP */
 
#define X86_FEATURE_LM   (2*32+29) /* Long Mode (x86-64) */
 
#define X86_FEATURE_3DNOWEXT   (2*32+30) /* AMD 3DNow! extensions */
 
#define X86_FEATURE_3DNOW   (2*32+31) /* 3DNow! */
 
#define X86_FEATURE_LAHF_LM   (3*32+ 0) /* LAHF/SAHF in long mode */
 
#define X86_FEATURE_CMP_LEGACY   (3*32+ 1) /* If yes HyperThreading not valid */
 
#define X86_FEATURE_SVM   (3*32+ 2) /* Secure virtual machine */
 
#define X86_FEATURE_EXTAPIC   (3*32+ 3) /* Extended APIC space */
 
#define X86_FEATURE_CR8_LEGACY   (3*32+ 4) /* CR8 in 32-bit mode */
 
#define X86_FEATURE_ABM   (3*32+ 5) /* Advanced bit manipulation */
 
#define X86_FEATURE_SSE4A   (3*32+ 6) /* SSE-4A */
 
#define X86_FEATURE_MISALIGNSSE   (3*32+ 7) /* Misaligned SSE mode */
 
#define X86_FEATURE_3DNOWPREFETCH   (3*32+ 8) /* 3DNow prefetch instructions */
 
#define X86_FEATURE_OSVW   (3*32+ 9) /* OS Visible Workaround */
 
#define X86_FEATURE_IBS   (3*32+10) /* Instruction Based Sampling */
 
#define X86_FEATURE_XOP   (3*32+11) /* extended AVX instructions */
 
#define X86_FEATURE_SKINIT   (3*32+12) /* SKINIT/STGI instructions */
 
#define X86_FEATURE_WDT   (3*32+13) /* Watchdog timer */
 
#define X86_FEATURE_LWP   (3*32+15) /* Light Weight Profiling */
 
#define X86_FEATURE_FMA4   (3*32+16) /* 4 operands MAC instructions */
 
#define X86_FEATURE_NODEID_MSR   (3*32+19) /* NodeId MSR */
 
#define X86_FEATURE_TBM   (3*32+21) /* trailing bit manipulations */
 
#define X86_FEATURE_TOPOEXT   (3*32+22) /* topology extensions CPUID leafs */
 
#define X86_FEATURE_DBEXT   (3*32+26) /* data breakpoint extension */
 
#define X86_FEATURE_MONITORX   (3*32+29) /* MONITOR extension (MONITORX/MWAITX) */
 
#define X86_FEATURE_XSAVEOPT   (4*32+ 0) /* XSAVEOPT instruction */
 
#define X86_FEATURE_XSAVEC   (4*32+ 1) /* XSAVEC/XRSTORC instructions */
 
#define X86_FEATURE_XGETBV1   (4*32+ 2) /* XGETBV with %ecx=1 */
 
#define X86_FEATURE_XSAVES   (4*32+ 3) /* XSAVES/XRSTORS instructions */
 
#define X86_FEATURE_FSGSBASE   (5*32+ 0) /* {RD,WR}{FS,GS}BASE instructions */
 
#define X86_FEATURE_TSC_ADJUST   (5*32+ 1) /* TSC_ADJUST MSR available */
 
#define X86_FEATURE_SGX   (5*32+ 2) /* Software Guard extensions */
 
#define X86_FEATURE_BMI1   (5*32+ 3) /* 1st bit manipulation extensions */
 
#define X86_FEATURE_HLE   (5*32+ 4) /* Hardware Lock Elision */
 
#define X86_FEATURE_AVX2   (5*32+ 5) /* AVX2 instructions */
 
#define X86_FEATURE_FDP_EXCP_ONLY   (5*32+ 6) /* x87 FDP only updated on exception. */
 
#define X86_FEATURE_SMEP   (5*32+ 7) /* Supervisor Mode Execution Protection */
 
#define X86_FEATURE_BMI2   (5*32+ 8) /* 2nd bit manipulation extensions */
 
#define X86_FEATURE_ERMS   (5*32+ 9) /* Enhanced REP MOVSB/STOSB */
 
#define X86_FEATURE_INVPCID   (5*32+10) /* Invalidate Process Context ID */
 
#define X86_FEATURE_RTM   (5*32+11) /* Restricted Transactional Memory */
 
#define X86_FEATURE_PQM   (5*32+12) /* Platform QoS Monitoring */
 
#define X86_FEATURE_NO_FPU_SEL   (5*32+13) /* FPU CS/DS stored as zero */
 
#define X86_FEATURE_MPX   (5*32+14) /* Memory Protection Extensions */
 
#define X86_FEATURE_PQE   (5*32+15) /* Platform QoS Enforcement */
 
#define X86_FEATURE_RDSEED   (5*32+18) /* RDSEED instruction */
 
#define X86_FEATURE_ADX   (5*32+19) /* ADCX, ADOX instructions */
 
#define X86_FEATURE_SMAP   (5*32+20) /* Supervisor Mode Access Prevention */
 
#define X86_FEATURE_PCOMMIT   (5*32+22) /* PCOMMIT instruction */
 
#define X86_FEATURE_CLFLUSHOPT   (5*32+23) /* CLFLUSHOPT instruction */
 
#define X86_FEATURE_CLWB   (5*32+24) /* CLWB instruction */
 
#define X86_FEATURE_SHA   (5*32+29) /* SHA1 & SHA256 instructions */
 
#define X86_FEATURE_PREFETCHWT1   (6*32+ 0) /* PREFETCHWT1 instruction */
 
#define X86_FEATURE_UMIP   (6*32+ 2) /* User-Mode Instruction Prevention */
 
#define X86_FEATURE_PKU   (6*32+ 3) /* Protection Keys for Userspace */
 
#define X86_FEATURE_OSPKE   (6*32+ 4) /* OS Protection Keys Enable */
 
#define X86_FEATURE_ITSC   (7*32+ 8) /* Invariant TSC */
 
#define X86_FEATURE_EFRO   (7*32+10) /* APERF/MPERF Read Only interface */
 
#define X86_FEATURE_CLZERO   (8*32+ 0) /* CLZERO instruction */
 

Macro Definition Documentation

◆ X86_FEATURE_FPU

#define X86_FEATURE_FPU   (0*32+ 0) /* Onboard FPU */

Definition at line 21 of file cpufeatureset.h.

◆ X86_FEATURE_VME

#define X86_FEATURE_VME   (0*32+ 1) /* Virtual Mode Extensions */

Definition at line 22 of file cpufeatureset.h.

◆ X86_FEATURE_DE

#define X86_FEATURE_DE   (0*32+ 2) /* Debugging Extensions */

Definition at line 23 of file cpufeatureset.h.

◆ X86_FEATURE_PSE

#define X86_FEATURE_PSE   (0*32+ 3) /* Page Size Extensions */

Definition at line 24 of file cpufeatureset.h.

◆ X86_FEATURE_TSC

#define X86_FEATURE_TSC   (0*32+ 4) /* Time Stamp Counter */

Definition at line 25 of file cpufeatureset.h.

◆ X86_FEATURE_MSR

#define X86_FEATURE_MSR   (0*32+ 5) /* Model-Specific Registers, RDMSR, WRMSR */

Definition at line 26 of file cpufeatureset.h.

◆ X86_FEATURE_PAE

#define X86_FEATURE_PAE   (0*32+ 6) /* Physical Address Extensions */

Definition at line 27 of file cpufeatureset.h.

◆ X86_FEATURE_MCE

#define X86_FEATURE_MCE   (0*32+ 7) /* Machine Check Architecture */

Definition at line 28 of file cpufeatureset.h.

◆ X86_FEATURE_CX8

#define X86_FEATURE_CX8   (0*32+ 8) /* CMPXCHG8 instruction */

Definition at line 29 of file cpufeatureset.h.

◆ X86_FEATURE_APIC

#define X86_FEATURE_APIC   (0*32+ 9) /* Onboard APIC */

Definition at line 30 of file cpufeatureset.h.

◆ X86_FEATURE_SEP

#define X86_FEATURE_SEP   (0*32+11) /* SYSENTER/SYSEXIT */

Definition at line 31 of file cpufeatureset.h.

◆ X86_FEATURE_MTRR

#define X86_FEATURE_MTRR   (0*32+12) /* Memory Type Range Registers */

Definition at line 32 of file cpufeatureset.h.

◆ X86_FEATURE_PGE

#define X86_FEATURE_PGE   (0*32+13) /* Page Global Enable */

Definition at line 33 of file cpufeatureset.h.

◆ X86_FEATURE_MCA

#define X86_FEATURE_MCA   (0*32+14) /* Machine Check Architecture */

Definition at line 34 of file cpufeatureset.h.

◆ X86_FEATURE_CMOV

#define X86_FEATURE_CMOV   (0*32+15) /* CMOV instruction (FCMOVCC and FCOMI too if FPU present) */

Definition at line 35 of file cpufeatureset.h.

◆ X86_FEATURE_PAT

#define X86_FEATURE_PAT   (0*32+16) /* Page Attribute Table */

Definition at line 36 of file cpufeatureset.h.

◆ X86_FEATURE_PSE36

#define X86_FEATURE_PSE36   (0*32+17) /* 36-bit PSEs */

Definition at line 37 of file cpufeatureset.h.

◆ X86_FEATURE_CLFLUSH

#define X86_FEATURE_CLFLUSH   (0*32+19) /* CLFLUSH instruction */

Definition at line 38 of file cpufeatureset.h.

◆ X86_FEATURE_DS

#define X86_FEATURE_DS   (0*32+21) /* Debug Store */

Definition at line 39 of file cpufeatureset.h.

◆ X86_FEATURE_ACPI

#define X86_FEATURE_ACPI   (0*32+22) /* ACPI via MSR */

Definition at line 40 of file cpufeatureset.h.

◆ X86_FEATURE_MMX

#define X86_FEATURE_MMX   (0*32+23) /* Multimedia Extensions */

Definition at line 41 of file cpufeatureset.h.

◆ X86_FEATURE_FXSR

#define X86_FEATURE_FXSR   (0*32+24) /* FXSAVE and FXRSTOR instructions */

Definition at line 42 of file cpufeatureset.h.

◆ X86_FEATURE_SSE

#define X86_FEATURE_SSE   (0*32+25) /* Streaming SIMD Extensions */

Definition at line 43 of file cpufeatureset.h.

◆ X86_FEATURE_SSE2

#define X86_FEATURE_SSE2   (0*32+26) /* Streaming SIMD Extensions-2 */

Definition at line 44 of file cpufeatureset.h.

◆ X86_FEATURE_HTT

#define X86_FEATURE_HTT   (0*32+28) /* Hyper-Threading Technology */

Definition at line 45 of file cpufeatureset.h.

◆ X86_FEATURE_TM1

#define X86_FEATURE_TM1   (0*32+29) /* Thermal Monitor 1 */

Definition at line 46 of file cpufeatureset.h.

◆ X86_FEATURE_PBE

#define X86_FEATURE_PBE   (0*32+31) /* Pending Break Enable */

Definition at line 47 of file cpufeatureset.h.

◆ X86_FEATURE_SSE3

#define X86_FEATURE_SSE3   (1*32+ 0) /* Streaming SIMD Extensions-3 */

Definition at line 50 of file cpufeatureset.h.

◆ X86_FEATURE_PCLMULQDQ

#define X86_FEATURE_PCLMULQDQ   (1*32+ 1) /* Carry-less mulitplication */

Definition at line 51 of file cpufeatureset.h.

◆ X86_FEATURE_DTES64

#define X86_FEATURE_DTES64   (1*32+ 2) /* 64-bit Debug Store */

Definition at line 52 of file cpufeatureset.h.

◆ X86_FEATURE_MONITOR

#define X86_FEATURE_MONITOR   (1*32+ 3) /* Monitor/Mwait support */

Definition at line 53 of file cpufeatureset.h.

◆ X86_FEATURE_DSCPL

#define X86_FEATURE_DSCPL   (1*32+ 4) /* CPL Qualified Debug Store */

Definition at line 54 of file cpufeatureset.h.

◆ X86_FEATURE_VMX

#define X86_FEATURE_VMX   (1*32+ 5) /* Virtual Machine Extensions */

Definition at line 55 of file cpufeatureset.h.

◆ X86_FEATURE_SMX

#define X86_FEATURE_SMX   (1*32+ 6) /* Safer Mode Extensions */

Definition at line 56 of file cpufeatureset.h.

◆ X86_FEATURE_EIST

#define X86_FEATURE_EIST   (1*32+ 7) /* Enhanced SpeedStep */

Definition at line 57 of file cpufeatureset.h.

◆ X86_FEATURE_TM2

#define X86_FEATURE_TM2   (1*32+ 8) /* Thermal Monitor 2 */

Definition at line 58 of file cpufeatureset.h.

◆ X86_FEATURE_SSSE3

#define X86_FEATURE_SSSE3   (1*32+ 9) /* Supplemental Streaming SIMD Extensions-3 */

Definition at line 59 of file cpufeatureset.h.

◆ X86_FEATURE_FMA

#define X86_FEATURE_FMA   (1*32+12) /* Fused Multiply Add */

Definition at line 60 of file cpufeatureset.h.

◆ X86_FEATURE_CX16

#define X86_FEATURE_CX16   (1*32+13) /* CMPXCHG16B */

Definition at line 61 of file cpufeatureset.h.

◆ X86_FEATURE_XTPR

#define X86_FEATURE_XTPR   (1*32+14) /* Send Task Priority Messages */

Definition at line 62 of file cpufeatureset.h.

◆ X86_FEATURE_PDCM

#define X86_FEATURE_PDCM   (1*32+15) /* Perf/Debug Capability MSR */

Definition at line 63 of file cpufeatureset.h.

◆ X86_FEATURE_PCID

#define X86_FEATURE_PCID   (1*32+17) /* Process Context ID */

Definition at line 64 of file cpufeatureset.h.

◆ X86_FEATURE_DCA

#define X86_FEATURE_DCA   (1*32+18) /* Direct Cache Access */

Definition at line 65 of file cpufeatureset.h.

◆ X86_FEATURE_SSE4_1

#define X86_FEATURE_SSE4_1   (1*32+19) /* Streaming SIMD Extensions 4.1 */

Definition at line 66 of file cpufeatureset.h.

◆ X86_FEATURE_SSE4_2

#define X86_FEATURE_SSE4_2   (1*32+20) /* Streaming SIMD Extensions 4.2 */

Definition at line 67 of file cpufeatureset.h.

◆ X86_FEATURE_X2APIC

#define X86_FEATURE_X2APIC   (1*32+21) /* Extended xAPIC */

Definition at line 68 of file cpufeatureset.h.

◆ X86_FEATURE_MOVBE

#define X86_FEATURE_MOVBE   (1*32+22) /* movbe instruction */

Definition at line 69 of file cpufeatureset.h.

◆ X86_FEATURE_POPCNT

#define X86_FEATURE_POPCNT   (1*32+23) /* POPCNT instruction */

Definition at line 70 of file cpufeatureset.h.

◆ X86_FEATURE_TSC_DEADLINE

#define X86_FEATURE_TSC_DEADLINE   (1*32+24) /* TSC Deadline Timer */

Definition at line 71 of file cpufeatureset.h.

◆ X86_FEATURE_AESNI

#define X86_FEATURE_AESNI   (1*32+25) /* AES instructions */

Definition at line 72 of file cpufeatureset.h.

◆ X86_FEATURE_XSAVE

#define X86_FEATURE_XSAVE   (1*32+26) /* XSAVE/XRSTOR/XSETBV/XGETBV */

Definition at line 73 of file cpufeatureset.h.

◆ X86_FEATURE_OSXSAVE

#define X86_FEATURE_OSXSAVE   (1*32+27) /* OSXSAVE */

Definition at line 74 of file cpufeatureset.h.

◆ X86_FEATURE_AVX

#define X86_FEATURE_AVX   (1*32+28) /* Advanced Vector Extensions */

Definition at line 75 of file cpufeatureset.h.

◆ X86_FEATURE_F16C

#define X86_FEATURE_F16C   (1*32+29) /* Half-precision convert instruction */

Definition at line 76 of file cpufeatureset.h.

◆ X86_FEATURE_RDRAND

#define X86_FEATURE_RDRAND   (1*32+30) /* Digital Random Number Generator */

Definition at line 77 of file cpufeatureset.h.

◆ X86_FEATURE_HYPERVISOR

#define X86_FEATURE_HYPERVISOR   (1*32+31) /* Running under some hypervisor */

Definition at line 78 of file cpufeatureset.h.

◆ X86_FEATURE_SYSCALL

#define X86_FEATURE_SYSCALL   (2*32+11) /* SYSCALL/SYSRET */

Definition at line 81 of file cpufeatureset.h.

◆ X86_FEATURE_NX

#define X86_FEATURE_NX   (2*32+20) /* Execute Disable */

Definition at line 82 of file cpufeatureset.h.

◆ X86_FEATURE_MMXEXT

#define X86_FEATURE_MMXEXT   (2*32+22) /* AMD MMX extensions */

Definition at line 83 of file cpufeatureset.h.

◆ X86_FEATURE_FFXSR

#define X86_FEATURE_FFXSR   (2*32+25) /* FFXSR instruction optimizations */

Definition at line 84 of file cpufeatureset.h.

◆ X86_FEATURE_PAGE1GB

#define X86_FEATURE_PAGE1GB   (2*32+26) /* 1Gb large page support */

Definition at line 85 of file cpufeatureset.h.

◆ X86_FEATURE_RDTSCP

#define X86_FEATURE_RDTSCP   (2*32+27) /* RDTSCP */

Definition at line 86 of file cpufeatureset.h.

◆ X86_FEATURE_LM

#define X86_FEATURE_LM   (2*32+29) /* Long Mode (x86-64) */

Definition at line 87 of file cpufeatureset.h.

◆ X86_FEATURE_3DNOWEXT

#define X86_FEATURE_3DNOWEXT   (2*32+30) /* AMD 3DNow! extensions */

Definition at line 88 of file cpufeatureset.h.

◆ X86_FEATURE_3DNOW

#define X86_FEATURE_3DNOW   (2*32+31) /* 3DNow! */

Definition at line 89 of file cpufeatureset.h.

◆ X86_FEATURE_LAHF_LM

#define X86_FEATURE_LAHF_LM   (3*32+ 0) /* LAHF/SAHF in long mode */

Definition at line 92 of file cpufeatureset.h.

◆ X86_FEATURE_CMP_LEGACY

#define X86_FEATURE_CMP_LEGACY   (3*32+ 1) /* If yes HyperThreading not valid */

Definition at line 93 of file cpufeatureset.h.

◆ X86_FEATURE_SVM

#define X86_FEATURE_SVM   (3*32+ 2) /* Secure virtual machine */

Definition at line 94 of file cpufeatureset.h.

◆ X86_FEATURE_EXTAPIC

#define X86_FEATURE_EXTAPIC   (3*32+ 3) /* Extended APIC space */

Definition at line 95 of file cpufeatureset.h.

◆ X86_FEATURE_CR8_LEGACY

#define X86_FEATURE_CR8_LEGACY   (3*32+ 4) /* CR8 in 32-bit mode */

Definition at line 96 of file cpufeatureset.h.

◆ X86_FEATURE_ABM

#define X86_FEATURE_ABM   (3*32+ 5) /* Advanced bit manipulation */

Definition at line 97 of file cpufeatureset.h.

◆ X86_FEATURE_SSE4A

#define X86_FEATURE_SSE4A   (3*32+ 6) /* SSE-4A */

Definition at line 98 of file cpufeatureset.h.

◆ X86_FEATURE_MISALIGNSSE

#define X86_FEATURE_MISALIGNSSE   (3*32+ 7) /* Misaligned SSE mode */

Definition at line 99 of file cpufeatureset.h.

◆ X86_FEATURE_3DNOWPREFETCH

#define X86_FEATURE_3DNOWPREFETCH   (3*32+ 8) /* 3DNow prefetch instructions */

Definition at line 100 of file cpufeatureset.h.

◆ X86_FEATURE_OSVW

#define X86_FEATURE_OSVW   (3*32+ 9) /* OS Visible Workaround */

Definition at line 101 of file cpufeatureset.h.

◆ X86_FEATURE_IBS

#define X86_FEATURE_IBS   (3*32+10) /* Instruction Based Sampling */

Definition at line 102 of file cpufeatureset.h.

◆ X86_FEATURE_XOP

#define X86_FEATURE_XOP   (3*32+11) /* extended AVX instructions */

Definition at line 103 of file cpufeatureset.h.

◆ X86_FEATURE_SKINIT

#define X86_FEATURE_SKINIT   (3*32+12) /* SKINIT/STGI instructions */

Definition at line 104 of file cpufeatureset.h.

◆ X86_FEATURE_WDT

#define X86_FEATURE_WDT   (3*32+13) /* Watchdog timer */

Definition at line 105 of file cpufeatureset.h.

◆ X86_FEATURE_LWP

#define X86_FEATURE_LWP   (3*32+15) /* Light Weight Profiling */

Definition at line 106 of file cpufeatureset.h.

◆ X86_FEATURE_FMA4

#define X86_FEATURE_FMA4   (3*32+16) /* 4 operands MAC instructions */

Definition at line 107 of file cpufeatureset.h.

◆ X86_FEATURE_NODEID_MSR

#define X86_FEATURE_NODEID_MSR   (3*32+19) /* NodeId MSR */

Definition at line 108 of file cpufeatureset.h.

◆ X86_FEATURE_TBM

#define X86_FEATURE_TBM   (3*32+21) /* trailing bit manipulations */

Definition at line 109 of file cpufeatureset.h.

◆ X86_FEATURE_TOPOEXT

#define X86_FEATURE_TOPOEXT   (3*32+22) /* topology extensions CPUID leafs */

Definition at line 110 of file cpufeatureset.h.

◆ X86_FEATURE_DBEXT

#define X86_FEATURE_DBEXT   (3*32+26) /* data breakpoint extension */

Definition at line 111 of file cpufeatureset.h.

◆ X86_FEATURE_MONITORX

#define X86_FEATURE_MONITORX   (3*32+29) /* MONITOR extension (MONITORX/MWAITX) */

Definition at line 112 of file cpufeatureset.h.

◆ X86_FEATURE_XSAVEOPT

#define X86_FEATURE_XSAVEOPT   (4*32+ 0) /* XSAVEOPT instruction */

Definition at line 115 of file cpufeatureset.h.

◆ X86_FEATURE_XSAVEC

#define X86_FEATURE_XSAVEC   (4*32+ 1) /* XSAVEC/XRSTORC instructions */

Definition at line 116 of file cpufeatureset.h.

◆ X86_FEATURE_XGETBV1

#define X86_FEATURE_XGETBV1   (4*32+ 2) /* XGETBV with %ecx=1 */

Definition at line 117 of file cpufeatureset.h.

◆ X86_FEATURE_XSAVES

#define X86_FEATURE_XSAVES   (4*32+ 3) /* XSAVES/XRSTORS instructions */

Definition at line 118 of file cpufeatureset.h.

◆ X86_FEATURE_FSGSBASE

#define X86_FEATURE_FSGSBASE   (5*32+ 0) /* {RD,WR}{FS,GS}BASE instructions */

Definition at line 121 of file cpufeatureset.h.

◆ X86_FEATURE_TSC_ADJUST

#define X86_FEATURE_TSC_ADJUST   (5*32+ 1) /* TSC_ADJUST MSR available */

Definition at line 122 of file cpufeatureset.h.

◆ X86_FEATURE_SGX

#define X86_FEATURE_SGX   (5*32+ 2) /* Software Guard extensions */

Definition at line 123 of file cpufeatureset.h.

◆ X86_FEATURE_BMI1

#define X86_FEATURE_BMI1   (5*32+ 3) /* 1st bit manipulation extensions */

Definition at line 124 of file cpufeatureset.h.

◆ X86_FEATURE_HLE

#define X86_FEATURE_HLE   (5*32+ 4) /* Hardware Lock Elision */

Definition at line 125 of file cpufeatureset.h.

◆ X86_FEATURE_AVX2

#define X86_FEATURE_AVX2   (5*32+ 5) /* AVX2 instructions */

Definition at line 126 of file cpufeatureset.h.

◆ X86_FEATURE_FDP_EXCP_ONLY

#define X86_FEATURE_FDP_EXCP_ONLY   (5*32+ 6) /* x87 FDP only updated on exception. */

Definition at line 127 of file cpufeatureset.h.

◆ X86_FEATURE_SMEP

#define X86_FEATURE_SMEP   (5*32+ 7) /* Supervisor Mode Execution Protection */

Definition at line 128 of file cpufeatureset.h.

◆ X86_FEATURE_BMI2

#define X86_FEATURE_BMI2   (5*32+ 8) /* 2nd bit manipulation extensions */

Definition at line 129 of file cpufeatureset.h.

◆ X86_FEATURE_ERMS

#define X86_FEATURE_ERMS   (5*32+ 9) /* Enhanced REP MOVSB/STOSB */

Definition at line 130 of file cpufeatureset.h.

◆ X86_FEATURE_INVPCID

#define X86_FEATURE_INVPCID   (5*32+10) /* Invalidate Process Context ID */

Definition at line 131 of file cpufeatureset.h.

◆ X86_FEATURE_RTM

#define X86_FEATURE_RTM   (5*32+11) /* Restricted Transactional Memory */

Definition at line 132 of file cpufeatureset.h.

◆ X86_FEATURE_PQM

#define X86_FEATURE_PQM   (5*32+12) /* Platform QoS Monitoring */

Definition at line 133 of file cpufeatureset.h.

◆ X86_FEATURE_NO_FPU_SEL

#define X86_FEATURE_NO_FPU_SEL   (5*32+13) /* FPU CS/DS stored as zero */

Definition at line 134 of file cpufeatureset.h.

◆ X86_FEATURE_MPX

#define X86_FEATURE_MPX   (5*32+14) /* Memory Protection Extensions */

Definition at line 135 of file cpufeatureset.h.

◆ X86_FEATURE_PQE

#define X86_FEATURE_PQE   (5*32+15) /* Platform QoS Enforcement */

Definition at line 136 of file cpufeatureset.h.

◆ X86_FEATURE_RDSEED

#define X86_FEATURE_RDSEED   (5*32+18) /* RDSEED instruction */

Definition at line 137 of file cpufeatureset.h.

◆ X86_FEATURE_ADX

#define X86_FEATURE_ADX   (5*32+19) /* ADCX, ADOX instructions */

Definition at line 138 of file cpufeatureset.h.

◆ X86_FEATURE_SMAP

#define X86_FEATURE_SMAP   (5*32+20) /* Supervisor Mode Access Prevention */

Definition at line 139 of file cpufeatureset.h.

◆ X86_FEATURE_PCOMMIT

#define X86_FEATURE_PCOMMIT   (5*32+22) /* PCOMMIT instruction */

Definition at line 140 of file cpufeatureset.h.

◆ X86_FEATURE_CLFLUSHOPT

#define X86_FEATURE_CLFLUSHOPT   (5*32+23) /* CLFLUSHOPT instruction */

Definition at line 141 of file cpufeatureset.h.

◆ X86_FEATURE_CLWB

#define X86_FEATURE_CLWB   (5*32+24) /* CLWB instruction */

Definition at line 142 of file cpufeatureset.h.

◆ X86_FEATURE_SHA

#define X86_FEATURE_SHA   (5*32+29) /* SHA1 & SHA256 instructions */

Definition at line 143 of file cpufeatureset.h.

◆ X86_FEATURE_PREFETCHWT1

#define X86_FEATURE_PREFETCHWT1   (6*32+ 0) /* PREFETCHWT1 instruction */

Definition at line 146 of file cpufeatureset.h.

◆ X86_FEATURE_UMIP

#define X86_FEATURE_UMIP   (6*32+ 2) /* User-Mode Instruction Prevention */

Definition at line 147 of file cpufeatureset.h.

◆ X86_FEATURE_PKU

#define X86_FEATURE_PKU   (6*32+ 3) /* Protection Keys for Userspace */

Definition at line 148 of file cpufeatureset.h.

◆ X86_FEATURE_OSPKE

#define X86_FEATURE_OSPKE   (6*32+ 4) /* OS Protection Keys Enable */

Definition at line 149 of file cpufeatureset.h.

◆ X86_FEATURE_ITSC

#define X86_FEATURE_ITSC   (7*32+ 8) /* Invariant TSC */

Definition at line 152 of file cpufeatureset.h.

◆ X86_FEATURE_EFRO

#define X86_FEATURE_EFRO   (7*32+10) /* APERF/MPERF Read Only interface */

Definition at line 153 of file cpufeatureset.h.

◆ X86_FEATURE_CLZERO

#define X86_FEATURE_CLZERO   (8*32+ 0) /* CLZERO instruction */

Definition at line 156 of file cpufeatureset.h.